cystech electronics corp. spec. no. : c563j3 issued date : 2012.01.16 revised date : 2012.10.11 page no. : 1/8 MTP4060J3 cystek product specification p-channel logic level enha ncement mode power mosfet MTP4060J3 features ? low gate charge ? simple drive requirement ? pb-free lead plating & halogen-free package equivalent circuit outline absolute maximum ratings (t c =25 c, unless otherwise noted) MTP4060J3 to-252(dpak) g gate d drain s source bv dss -100v i d -27a r dson @v gs =-10v, i d =-20a 36m (typ.) r dson @v gs =-4.5v, i d =-18a 41m (typ.) g d s parameter symbol limits unit drain-source voltage v ds -100 v gs 20 v gate-source voltage i d -27 continuous drain current @ t c =25 c i d -19 continuous drain current @ t c =100 c pulsed drain current *1 i dm -108 i as -20 a avalanche current avalanche energy @ l=0.1mh, i d =-20a, r g =25 e as 20 mj total power dissipation @t c =25 60 pd w total power dissipation @t c =100 30 operating junction and storage te mperature range tj, tstg -55~+175 c note : *1 . pulse width limited by maximum junction temperature *2. duty cycle 1%
cystech electronics corp. spec. no. : c563j3 issued date : 2012.01.16 revised date : 2012.10.11 page no. : 2/8 MTP4060J3 cystek product specification thermal data parameter symbol value unit thermal resistance, junction-to-case, max r th,j-c 2.5 c/w thermal resistance, junction-to-ambient, max r th,j-a 50 (note) c/w thermal resistance, junction-to-ambient, max r th,j-a 110 c/w note : when mounted on the minimu m pad size recommended (pcb mount). characteristics (tc=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss -100 - - v v gs =0v, i d =-250 a v gs(th) -1 -1.9 -3 v v ds =v gs , i d =-250 a g fs *1 - 72 - s v ds =-10v, i d =-20a i gss - - 100 na v gs = 20, v ds =0v - - -1 v ds =-100v, v gs =0v i dss - - -10 a v ds =-100v, v gs =0v, tj=125 c - 36 45 v gs =-10v, i d =-20a r ds(on) *1 - 41 50 m v gs =-4.5v, i d =-18a dynamic qg *1, 2 - 152 - qgs *1, 2 - 28 - qgd *1, 2 - 80 - nc i d =-27a, v ds =-50v, v gs =-10v t d(on) *1, 2 - 70 - tr *1, 2 - 15 - t d(off) *1, 2 - 136 - t f *1, 2 - 60 - ns v ds =-20v, i d =-1a, v gs =-10v, r g =6 ciss - 8233 - coss - 234 - crss - 166 - pf v gs =0v, v ds =-25v, f=1mhz source-drain diode i s *1 - - -27 i sm *3 - - -108 a v sd *1 - - -1.2 v i f =-20a, v gs =0v trr - 180 - ns qrr - 1.3 - c i f =i s , di f /dt=100a/ s note : *1.pulse test : pulse width 300 s, duty cycle 2% *2.independent of operating temperature *3.pulse width limited by maximum junction temperature. ordering information device package shipping MTP4060J3-0-t3-g to-252 (pb-free lead plating & halogen-free package) 2500 pcs / tape & reel
cystech electronics corp. spec. no. : c563j3 issued date : 2012.01.16 revised date : 2012.10.11 page no. : 3/8 MTP4060J3 cystek product specification typical characteristics typical output characteristics 0 20 40 60 80 100 120 140 160 180 024681 0 brekdown voltage vs ambient temperature 0.4 0.6 0.8 1 1.2 1.4 -100 -50 0 50 100 150 200 tj, junction temperature(c) -bv dss , normalized drain-source breakdown voltage i d =-250 a, v gs =0v -v ds , drain-source voltage(v) -i d , drain current(a) 10v 9v 8v 7v 6v 5v -v gs =4v -v gs =3v -v =2v gs static drain-source on-state resistance vs drain current 10 100 1000 10000 0.001 0.01 0.1 1 10 100 -i d , drain current(a) r ds( on) , static drain-source on-state resistance(m) v gs =-2.5v v gs =-3v v gs =-4.5v v gs =-10v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 0 5 10 15 20 -i dr , reverse drain current(a) -v sd , source-drain voltage(v) tj=25c tj=150c v gs =0v static drain-source on-state resistance vs gate-source voltage 0 40 80 120 160 200 240 280 320 360 400 024681 0 drain-source on-state resistance vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -60 -20 20 60 100 140 180 tj, junction temperature(c) r ds( on) , normalized static drain- source on-state resistance v gs =-10v, i d =-20a r dson @tj=25c : 35.6m -v gs , gate-source voltage(v) r ds( on) , static drain-source on- state resistance(m) i d =-20a
cystech electronics corp. spec. no. : c563j3 issued date : 2012.01.16 revised date : 2012.10.11 page no. : 4/8 MTP4060J3 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 100 1000 10000 0.1 1 10 100 -v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 -60 -20 20 60 100 140 tj, junction temperature(c) -v gs( th) , normalized threshold voltage i d =-250ua maximum safe operating area 0.1 1 10 100 1000 0.1 1 10 100 1000 -v ds , drain-source voltage(v) -i d , drain current(a) dc 10ms 100ms 1ms 100 s 10 s r ds( on) limit t c =25c, tj=150, v gs =-10v single pulse gate charge characteristics 0 2 4 6 8 10 0 20 40 60 80 100 120 140 160 qg, total gate charge(nc) -v gs , gate-source voltage(v) v ds =-50v i d =-27a forward transfer admittance vs drain current 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100 -i d , drain current(a) g fs , forward transfer admittance(s) v ds =-10v pulsed ta=25c maximum drain current vs case temperature 0 5 10 15 20 25 30 35 25 50 75 100 125 150 175 200 t c , case temperature(c) -i d , maximum drain current(a) vgs=-10v, r jc =2.5c/w
cystech electronics corp. spec. no. : c563j3 issued date : 2012.01.16 revised date : 2012.10.11 page no. : 5/8 MTP4060J3 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 20 40 60 80 100 120 140 160 180 200 0246810 -v gs , gate-source voltage(v) -i d , drain current(a) v ds =-10v power derating curve 0 10 20 30 40 50 60 70 0 25 50 75 100 125 150 175 200 t c , case temperature() p d , power dissipation(w) transient thermal response curves 0.01 0.1 1 10 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 t 1 , square wave pulse duration(s) z jc (t), thermal response single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.z jc (t)=2.5 c/w max. 2.duty factor, d=t 1 /t 2 3.t jm -t c =p dm *z jc (t)
cystech electronics corp. spec. no. : c563j3 issued date : 2012.01.16 revised date : 2012.10.11 page no. : 6/8 MTP4060J3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c563j3 issued date : 2012.01.16 revised date : 2012.10.11 page no. : 7/8 MTP4060J3 cystek product specification recommended wave soldering condition soldering time product peak temperature pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds ? time(ts min to ts max ) time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c563j3 issued date : 2012.01.16 revised date : 2012.10.11 page no. : 8/8 MTP4060J3 cystek product specification to-252 dimension inches millimeters marking: 1 device name date code 4060 4 2 3 style: pin 1.gate 2.drain 3.source 4.drain 3-lead to-252 plastic surface mount package cystek package code: j3 inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.087 0.094 2.200 2.400 e 0.086 0.094 2.186 2.386 a1 0.000 0.005 0.000 0.127 e1 0.172 0.188 4.372 4.772 b 0.039 0.048 0.990 1.210 h 0.163 ref 4.140 ref b 0.026 0.034 0.660 0.860 k 0.190 ref 4.830 ref b1 0.026 0.034 0.660 0.860 l 0.386 0.409 9.800 10.400 c 0.018 0.023 0.460 0.580 l1 0.114 ref 2.900 ref c1 0.018 0.023 0.460 0.580 l2 0.055 0.067 1.400 1.700 d 0.256 0.264 6.500 6.700 l3 0.024 0.039 0.600 1.000 d1 0.201 0.215 5.100 5.460 p 0.026 ref 0.650 ref e 0.236 0.244 6.000 6.200 v 0.211 ref 5.350 ref notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead : pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
|
